![]() ![]() Therefore, it can be used to remove obfuscation that uses constants created by hardware opaque predicates regardless of how stealthy they are. Our approach is not impacted by the level of stealthiness of the constant values or the circuit that generates them. We demonstrate that, by assuring the full controllability of each input of each instantiated LUT in a design via iterative LUT modification, we can defeat obfuscation based on constant values and potentially unlock bitstreams locked using combinational logic locking . In this paper, we focus on FPGA obfuscation techniques that make use of constant values to change the function implemented in underutilised LUTs without changing their behavior during execution. ![]() injection of redundant combinational logic). Typically this is accomplished by redundancy addition (e.g. In the future, when AI algorithms become a natural part of many systems, the extraction of neural network models from FPGA bitstreams through reverse engineering, or the tampering of the neural networks through bitstream modification, can pose a serious threat.Ī popular method of defense against bitstream reverse engineering and modification is to conceal the design’s functionality using obfuscation techniques. trojan injection, secret key recovery, and intellectual property theft. The adversary is typically assumed to be able to reverse engineer the bitstream to a certain degree and the goal of the attack is to recover and/or manipulate the logic of a given design to meet various ends, e.g. According to the design flow stages presented in , the adversary can acquire a bitstream during the bitstream-at-rest and bitstream-loading stages. These attacks assume an adversary that has access to the bitstream of a design under attack. It has been demonstrated that, with bitstream modification, it is possible to recover the secret key from FPGA implementations of cryptographic algorithms . Reverse engineering can lead to intellectual property theft and facilitate bitstream modification attacks. This fact renders bitstreams particularly vulnerable to threats such as reverse engineering and modification. The bitstream has to be loaded to the device at every power-on due to the volatile nature of SRAM. The programming of SRAM FPGAs is performed through a file called bitstream that contains the configuration information describing a given design in a hidden and proprietary format. This growth in popularity, however, gives rise to SRAM FPGA-specific security challenges. Therefore, SRAM FPGAs are a very attractive choice for many computationally heavy applications such as cryptographic algorithm implementation and AI acceleration. On the other hand, SRAM FPGAs offer lower performance and consume more power compared to ASICs but they require lower engineering effort and most importantly hold the advantage of reconfigurability making them a very agile device with low time to market. Furthermore, they require high engineering effort to design and their cost per chip becomes viable only for large chip orders making them an expensive solution for small companies and startups. However, they are severely lacking in agility, having a constant configuration and a very slow time to market. ASICs have an excellent performance and power consumption profile which can offer a very efficient acceleration. Two popular candidates for this role are application-specific integrated circuits (ASICs) and static random access memory field-programmable gate arrays (SRAM FPGAs). This can be offered through hardware acceleration. These technologies have an increasing demand for more powerful, low-power, agile, and low-cost devices. Our world is being transformed by the fourth industrial revolution which is marked by the rapid development and integration of life-changing technologies such as cloud computing, artificial intelligence (AI), and the internet of things (IoT). ![]()
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